1. Field of the Invention
The present invention relates to a data line driver circuit of a display panel, and a method of testing the same. This Patent application is based on Japanese Patent Application No. 2007-051359. The disclosure thereof is incorporated herein by reference.
2. Description of Related Art
A liquid crystal display apparatus will be described below with reference to FIG. 1. The liquid crystal display apparatus 100 is used as a display apparatus such as a mobile phone, a mobile terminal equipment, a note type of personal computer, a desktop type of personal computer and a television. As shown in FIG. 1, the liquid crystal display apparatus 100 contains a liquid crystal display panel 101, a data line driver circuit 102, a scanning line drive circuit 103, a power source 104 and a control circuit 105. The liquid crystal display panel 101 includes data lines 106 arranged to extend in a longitudinal direction, and scanning lines 107 arranged to extend in a lateral direction. Each of pixels includes a TFT (Thin Film Transistor) 108, a pixel capacitor 109 and a liquid crystal element 110. The gate terminal of the TFT 108 is connected to the scanning line 107, and the source (drain) electrode thereof is connected to the data line 106, respectively. Also, each of the pixel capacitor 109 and the liquid crystal element 110 is connected to the drain (source) electrode of the TFT 108. In the pixel capacitor 109 and the liquid crystal element 110, a terminal 111 that is not connected to the TFT 108 is connected to a common electrode (not shown). The data line driver circuit 102 outputs an image signal having a voltage determined based on a display data to drive the data line 106. The scanning line drive circuit 103 outputs a selection/non-selection voltage of the TFT 108 to drive the scanning line 107. The control circuit 105 controls the drive timings of the scanning line drive circuit 103 and the data line driver circuit 102. The power source 104 generates a signal voltage outputted from the data line driver circuit 102 and the power supply voltage used to generate the selection/non-selection voltage outputted from the scanning line drive circuit 103, and supplies to the respective driving circuits 102 and 103.
In this type of the liquid crystal display apparatus, a field inversion, a line inversion, a column inversion and a dot inversion are known as a method of alternately driving (or inversely driving) the display panel. The field inversion method is a method of setting the entire screen of the display panel to a same polarity and inverting it for each frame. The line inversion method is a method of setting to an opposite polarity for each column (scanning line) and inverting. The column inversion method is a method of setting to an opposite polarity for each row (data line) and inverting. The dot inversion method is a method of combining the line inversion and the column inversion and inverting in a checker-wise pattern. Among those methods, usually, the column inversion and the dot inversion are alternately driven by a common constant driving method. The common constant driving method is a driving method of keeping the voltage of a common electrode of a pixel constant and inverting the polarity of only the image signal from the data line driver circuit. Also, in case of the column inversion and the dot inversion, the data line driver circuit has a function of applying two kinds of image signals whose polarities are different to the plurality of data lines at the same time. The polarities of the image signal are defined as a positive polarity and a negative polarity with respect to a predetermined reference voltage (hereinafter, referred to as a “common level”). The common level is usually set close to a voltage equal to ½ of a high power supply voltage VDD of the data line driver circuit. It should be noted that the voltage of the common electrode is set to a voltage different from the common level for a field through correction for a display panel.
FIG. 2 is a block diagram showing the data line driver circuit used in the dot inversion method. The data line driver circuit in FIG. 2 includes a shift register circuit 112, a data register circuit 113, a data latch circuit 114, a level shifter circuit 115, a D/A (digital/analog) converter circuit 116 and an output circuit 117. The data line driver circuit shown in FIG. 2 is of a type that 2-system circuits are provided to alternately output positive and negative voltages. That is, in accordance with a polarity inversion signal, the positive and negative voltages with respect to the common level are alternately outputted in odd-numbered outputs and even-numbered outputs, to alternately drive the liquid crystal display panel while a relation between the positive and negative amplitudes is kept. In FIG. 2, the data register circuit 113 latches the display data (Dm, Dm-1, . . . , Dk, . . . , D2 and D1) of m (natural number) bits in parallel in response to the output from the shift register circuit 112. The data latch circuit 114 collectively latches the m-bit display data from the data register circuit 113 in response to a data latch signal. The data line driver circuit of the type shown in FIG. 2 generates a 2m-bit double-bit display data (Dm, DmB, Dm-1, Dm-1B, . . . , Dk, DkB, . . . , D2, D2B, D1 and D1B) from the latched m-bit display data (Dm, Dm-1, . . . , Dk, . . . , D2 and D1). Here, when Dk=“H”, DkB=“L”, and when Dk=“L”, DkB=“H”. Thus, as an information amount, there are still the m bits (K=1, 2, . . . , m). For the 2m-bit double-bit display data, the level shifter circuit 115 boosts up a voltage value. The D/A converter circuit 116 selects a desirable gradation voltage from 2m gradation voltages in accordance with the 2m-bit double-bit display data. In the output circuit 117, the selected gradation voltage is amplified by an operational amplifier and outputted. In FIG. 2, 2n m-bit display data are supplied to the data line driver circuit, and 2n image signals S2n, S2n−1, S2n−2, . . . , S2 and S1 are outputted. In the type of the positive and negative 2-system circuits, there are the even-numbered display data and output image signals.
FIG. 3 is a block diagram showing the D/A converter circuit 116. The gradation voltage supplied from the power source 104 is converted to a gradation voltage in which the non-linearity of the transmittance of the liquid crystal element 110 is corrected by a γ correction resistor section 118. In FIG. 3, the 2m positive gradation voltages and the 2m negative gradation voltages are generated. Any one of the generated positive gradation voltages is selected by a positive gradation voltage selecting circuit (PchDAC) 119 for receiving the 2m-bit double-bit display data. Also, any one of the generated negative gradation voltages is selected by a negative gradation voltage selecting circuit (NchDAC) 120 for receiving the 2m-bit double-bit display data. The selected gradation voltage is outputted from the output circuit 117 through a switch 121 and operational amplifiers 122 and 123. When the switch 121 is in a straight state, the positive gradation voltages appear in the odd-numbered outputs S2n−1, S2n−3, S2n−5, . . . , S1, and the negative gradation voltages appear in the even-numbered outputs S2n, S2n−2, S2n−4, . . . , S2. Also, when the switch 121 is in a cross state, the negative gradation voltages appear in the odd-numbered outputs S2n−1, S2n−3, S2n−5, . . . , S1, and the positive gradation voltages appear in the even-numbered outputs S2n, S2n−2, S2n−4, . . . , S2. The gradation voltage is selected for each scanning line 107 and outputted as the image signal to the data line 106. When the scanning lines 107 are driven for one cycle, one frame (one screen) is displayed.
When a characteristic test of the data line driver circuit is carried out, there is a problem in leakage current in the gradation voltage selecting circuit whose circuit scale is large. As for the characteristic test of the gradation voltage selecting circuit, Japanese Patent Application Publication (JP-A-Heisei 11-264855) is known. This conventional example contains a resistor ladder in which a predetermined number of resistors are connected in series, a correction power supply voltage is supplied to at least one of connection nodes between the resistors, to generate the gradation voltages in all of the connection nodes. Also, this contains an ROM decoder for supplying a data and selecting one of the gradation voltages from the ladder resistor. Also, this conventional example contains a test circuit for measuring leakage current from a ROM decoder. Moreover, this conventional example has a short-circuit circuit for electrically short-circuiting a predetermined number of resistors, when the test circuit measures the leakage current.
In the above conventional example, the switch is provided between the γ correction resistor section and the gradation voltage selecting circuit, and the switch is used to separate the γ correction resistor section and the test of the gradation voltage selecting circuit is carried out. However, although the test can measure the leakage current between the gate and the source of a transistor in the gradation voltage selecting circuit, the test cannot measure the leakage current between the drain and the source.